BYPASS_CLK_SRC=REF_CLK_24M, ENET2_DIV_SELECT=ENET2_DIV_SELECT_0
Analog ENET PLL Control Register
| DIV_SELECT | Controls the frequency of the ethernet reference clock |
| ENET2_DIV_SELECT | Controls the frequency of the ENET2 reference clock. 0 (ENET2_DIV_SELECT_0): 25MHz 1 (ENET2_DIV_SELECT_1): 50MHz 2 (ENET2_DIV_SELECT_2): 100MHz (not 50% duty cycle) 3 (ENET2_DIV_SELECT_3): 125MHz |
| POWERDOWN | Powers down the PLL. |
| ENABLE | Enable the PLL providing the ENET reference clock. |
| BYPASS_CLK_SRC | Determines the bypass source. 0 (REF_CLK_24M): Select the 24MHz oscillator as source. 1 (CLK1): Select the CLK1_N / CLK1_P as source. |
| BYPASS | Bypass the PLL. |
| ENET2_REF_EN | Enable the PLL providing the ENET2 reference clock |
| ENET_25M_REF_EN | Enable the PLL providing ENET 25 MHz reference clock |
| LOCK | 1 - PLL is currently locked; 0 - PLL is not currently locked. |